1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to a technique effective in application to a semiconductor device including a plurality of semiconductor chips.
2. Description of the Related Art
In conventional semiconductor devices (multichip modules) having multiple semiconductor chips, of three chips mounted on the main surface of the package board, a chip having a dynamic random access memory (DRAM) and a chip having a flash memory are each electrically connected to the wire of the package board via an Au bump. On the two chips, a chip having a high speed microprocessor is mounted and electrically connected to a bonding pad of the package board via an Au wire (e.g., refer to Patent Document 1: IP No. WO 02/103793, Ver. A1 (FIG. 2)).
Conventional memory modules including multiple semiconductor memory chips on the interconnection board include two or more layered chips such that the outputconnection of one chip intersects another chip directly thereunder so as to cross it. (e.g., refer to Patent Document 2: JP-A-5-121643 (FIG. 1)).
It is known in the art to provide a semiconductor device called a system-in-package (SIP) in which a semiconductor chip (hereinafter, referred to as a microcomputer chip) having an arithmetic processing function and a semiconductor chip having a memory circuit (hereinafter, referred to as a memory chip) are mounted on a wiring board.
The need for mass-storage memory of semiconductor devices has arisen as the users' demand for processing a high volume of data grows, and in addition, miniaturization of semiconductor devices is required to mount the semiconductor devices on compact electronic equipment.
Realizing high capacity of the memory with one chip increases the chip size, posing the problem of increasing the wiring board too, thus hindering the miniaturization of the semiconductor devices.
Accordingly, the present inventor studied a stack structure of memories of the same type to achieve the mass storage of memories and the miniaturization of semiconductor devices.
Patent Document 2 describes the stack structure of memory chips on a wiring board but does not describe the wiring layout of the wiring board at all.